hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 179

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

When SMCP applies, the number of active mode Control Word bits is reduced:
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un-
changed unless specifically indicated by an “SR” value.
Bit No. Mnemonic RW
MSB
MSB
15
14
13
15 14 13 12 11 10 9
15 14 13 12 11 10 9
H
H
IXEQZ
IWA
IBR
H
H
H
H
H
H
D1
D1
D
X
D
D
Reset
D
D
8
8
0
0
0
X
7
X
7
X
X
6
6
Function
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables
generation of an interrupt for mode code commands using indexed buffer
mode when the INDX value decrements from 1 to 0. Upon completion of
command processing that results in INDX = 0, when IXEQZ interrupts are
enabled, an IXEQZ interrupt is entered in the Pending Interrupt Register, the
INTMES output pin is asserted, and the interrupt is registered in the Interrupt
Log.
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high, assertion of this bit enables
interrupt generation at each instance of a valid mode code command. Upon
completion of command processing, when IWA interrupts are enabled, an
IWA interrupt is entered in the Pending Interrupt Register, the INTMES output
pin is asserted, and the interrupt is registered in the Interrupt Log.
Interrupt Broadcast Received.
If the Interrupt Enable Register IBR bit is high, assertion of this bit enables
interrupt generation at each instance of a valid broadcast transmit mode code
command. Upon completion of command processing, when IBR interrupts
are enabled, an IBR interrupt is entered in the Pending Interrupt Register, the
INTMES output pin is asserted, and the interrupt is registered in the Inter-
rupt Log. This bit has no function if the BCSTINV bit is high in Configuration
Register 1. In this case, commands to RT address 31 are not recognized as
valid by the device.
X
X
5
5
HOLT INTEGRATED CIRCUITS
X
X
4
4
HI-6130, HI-6131
H
X
3
3
H
X
2
2
X
X
1
1
X
X
0
0
179
LSB
LSB
D1
D1
H
D
H
D
X
X
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1