hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 151

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

18.10. Remote Terminal 1 (RT1) Built-In Test (BIT) Word Register (0x001E)
Bits 11-6 in these 16-bit registers are read-write; the remaining bits are read-only. The ten assigned bits are written
by the device when predetermined events occur. The host may overwrite the device-written bits 5 and 4. After MR
pin master reset, bits 13-12, 5-4 and 0 are reset. Bits 15-14 will be set if the corresponding TXINHA or TXINHB input
pins are high. Bits 3-1 will be set if RT address parity error, or post-MR memory test failure or auto-initialization failure
occurred. These registers are not affected by assertion of RTxRESET remote terminal software reset in the Master
Status and Reset Register (0x0001). Remote terminals RT1 and RT2 use independent BIT Word registers.
If the ALTBITW option bit in the RT Configuration Register is zero when a valid “transmit BIT word” mode command
(MC19) is received, the current value in this register is transmitted as the mode data word in the terminal response.
The value is also copied to the Remote Terminal’s assigned data buffer for MC19, after mode command fulfillment.
15 14 13 12 11 10 9
Bit No.
P
11 − 6
15
14
13
12
5
4
3
P
R
Remote Terminal 2 (RT2) Built-In Test (BIT) Word Register (0x0027)
0
Mnemonic
TXASD
TXBSD
RXASD
RXBSD
----------
BLBFA
BLBFB
BMTF
0
0
User Assigned Bits
0
0
RW
8
0
R/W
R/W
R
R
R
R
7
0
0
6
Reset
0
5
0
0
0
0
0
4
0
0
3
HOLT INTEGRATED CIRCUITS
R
Function
Transmit Bus A Shutdown.
Transmit Bus B Shutdown.
These read-only bits are set when the corresponding bus transmitter
was disabled by assertion of the bus TXINHA or TXINHB input pin, or
by fulfillment of a “transmitter shutdown” mode command, either MC4
or MC20. Refer to the description for the BSDTXO bit in the Master
Configuration Register (pg xx) and the description for the AUTOBSD bit
in the RT Configuration Register for further information.
Receive Bus A Shutdown.
Receive Bus B Shutdown.
These read-only bits are set when the corresponding bus receiver was
disabled concurrently with a bus transmitter by a “transmitter shutdown”
mode command MC4 or MC20. Refer to the description for the BSDTXO
bit in the Master Configuration Register (Section 9.1) and the description
for the AUTOBSD bit in the RT Configuration Register for further
information.
User assigned bits.
Bus A Loopback Fail.
Bus B Loopback Fail.
These read-only bits are set if Bus A or Bus B loopback failure occurs
during self-test.
BIST Memory Test Fail.
This bit is set if error occurs during built-in self-test for device Random
Access Memory (RAM).
0
2
HI-6130, HI-6131
0
1
0
0
MR Reset
Host Access
Bit
151