hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 133

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which
is when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message
data is stored in “data packets” in the monitor stack. If the elapsed time between successive MIL-STD-1553 words
(measured in 10 µs increments) reaches the value in this register, the HI-613x IMT finalizes an unfinished packet. The
maximum time interval is 655.35ms. The measured interval restarts after each Manchester word, and ends with gap
time-out, or detection of the next-occurring valid Manchester word on either bus. Under normal circumstances, this
register is used for determination of gaps between MIL-STD-1553 messages, however message fragments containing
valid Manchester words also preempt time-out and restart the timer.
16.8.1. Practical IRIG-106 maximum gap time considerations
Word validation occurs about 3us after Manchester word completion. When the programmed value in this register is
N, the in-process packet will finalize at (10N + 3) µs, unless a valid Manchester word started before the maximum
bus “dead time” of (N-2) x 10 µs. When the stored register value is zero, this register is not used for end-of-packet
determination.
Example: This register contains 20 decimal. The resultant maximum allowed bus “dead time” between Manchester
words is 180 µs. When gap time exceeds this limit, packet finalization occurs at 203 µs, and (if enabled) MT interrupts
occur for Packet Ready and Maximum Gap Time. A valid Manchester word starting after 180 µs is not included the
finalized packet, but may be the first word in the following packet when bits 6-5 in the MT Configuration Register equal
0-0 or 0-1.
16.9. IMT Packet Header Channel ID Register (0x002E)
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register is only used when the MT is configured for IRIG-106 Chapter 10 operational mode, with automatic
packet header and packet trailer generation. That is, when IMT bit 0 is initialized to logic 0, and IMTHTD bit 3 is
initialized to logic 1 in the MT Configuration Register 0x0029.
The IRIG-106 Chapter 10 packet header includes a 16-bit Channel ID. The value contained in this register is used for
the Channel ID field, when generating the packet header. The host must load a nonzero value into this register during
initialization because Channel ID of 0x0000 is reserved for computer-generated data packets.
MSB
15 14 13 12 11 10
0
0
0
0
0
0
Register Value
0
9
0
8
RW
7
0
0
6
0
5
4
0
0
3
HOLT INTEGRATED CIRCUITS
0
2
HI-6130, HI-6131
0
1
LSB
0
0
MR Reset
Host Access
Bit
133