hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 152

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

18.11. Remote Terminal 1 (RT1) Alternate Built-In Test (BIT) Word Register (0x001F)
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
It is not affected by assertion of RTxRESET remote terminal software reset in the Master Status and Reset Register
(0x0001). If the ALTBITW option bit in the RT Configuration Register equals one when a valid “transmit BIT word” mode
command (MC19) is received, the current value in this register is transmitted as the mode data word in the terminal
response. The value is also copied to the assigned data buffer for MC19, after mode command fulfillment.
18.12. Remote Terminal 1 (RT1) Time Tag Counter Register (0x0049)
This register is read-only and is cleared after MR pin Master Reset or assertion of RTxRESET remote terminal software
reset in the Master Status and Reset Register (0x0001). Reads to this register address return the current value of
the free running 16-bit Time Tag counter. Counter resolution is programmed by the TTCK2:0 bits in the Time Tag
Configuration Register. Options are: 2, 4, 8, 16, 32 and 64µs, or externally provided clock. The same clock source is
shared by RT1, RT2 and the BC.
MSB
MSB
Bit No.
15 14 13 12 11 10
15 14 13 12 11 10
0
0
2
1
0
0
0
Remote Terminal 2 (RT2) Alternate Built-In Test (BIT) Word Register (0x0028)
Remote Terminal 2 (RT2) Time Tag Counter Register (0x004B)
0
0
Mnemonic
RTAPF
EELF
TFBINH
0
0
0
0
0
0
Register Value
Register Value
0
9
0
9
0
8
0
8
R/W
RW
R
R
R
R
7
7
0
0
0
6
0
6
Reset
0
0
5
5
0
0
0
4
4
0
0
0
3
0
3
HOLT INTEGRATED CIRCUITS
Function
RT Address Parity Fail.
This bit is asserted when an RT1 or RT2 Operational Status Register
bits 15:10 reflect parity error. After MR master reset, bits 15:10 in the
RT’s Operational Status Register reflect input pin states, but will be
overwritten if subsequent auto-initialization is performed (if AUTOEN
pin is high) and the initialization EEPROM contains different data for RT
Operational Status Register bits 15:10.
Auto-Initialization EEPROM Load Fail.
This bit only applies when auto-initialization is enabled (AUTOEN input
pin state equals 1). This bit is set if, after MR master reset, failure occurs
when copying serial EEPROM to registers and RAM. When this occurs,
bit 0 or bit 1 will be set in the RT’s Operational Status Register (0x0002)
to indicate type of failure.
This bit is set when the Terminal Flag status bit is disabled while fulfilling
an “inhibit terminal flag bit” mode code command (MC6). This bit is reset
if terminal flag status bit disablement is cancelled later by an “override
inhibit terminal flag bit” mode code command (MC7).
0
0
2
2
HI-6130, HI-6131
0
1
0
1
LSB
LSB
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
152