hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 231

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

25. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS
* Terminal is using “illegal command detection” and command is legal
** Terminal is using “illegal command detection” and command is illegal.
Circumstances for
Received Message
Invalid Command
Word (Manchester,
parity or bit count error)
Any valid command
to RT31 (broadcast).
when the BCSTINV
bit in Configuration
Register 1 equals 1.
RT Address Parity Error
based on RTA and
RTAP
bits in the Operational
Status Register
Any valid non-mode
(subaddress 1-30)
transmit command
to RT31 (undefined
broadcast transmit).
Any valid non-mode
(subaddress 1-30)
transmit command
except for RT31. The
corresponding bit
in the Illegalization
Table equals 0.*
Any valid non-mode
(subaddress 1-30)
transmit command
except for RT31. The
corresponding bit
in the Illegalization
Table equals 1. **
Any valid non-mode
(subaddress 1-30)
receive command.
The corresponding
bit in the Illegalization
Table equals 0. *
OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response).
Terminal Response to
Received Command
No terminal response,
the message is ignored.
No Status Word change.
No terminal response,
the message is ignored.
No Status Word change.
(Broadcast commands
For commands to the RT’s
own address or to broadcast
address RT31: No terminal
response, message is ignored.
No Status Word change.
No terminal response,
Set Message Error (ME)
and BCR status bits.
Normal Status Word response
(Clear Status). Data words for
transmit are read from the
RAM data buffer assigned
by the Descriptor Table entry
for the transmit subaddress.
Assert Message Error (ME)
status, then transmit
ME Status Word
without following data words.
Normal Status Word response
(Clear Status). After message
completion, the data words
received are stored in the data
buffer RAM location assigned
by the Descriptor Table entry
for the receive subaddress.
are rendered invalid.)
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
231
Bits Updated
in Descriptor
Control Word
No change
No change
No change
DBAC bit set.
DPB bit toggles.
BCAST bit set.
DBAC bit set.
DPB bit toggles.
BCAST bit reset.
DBAC bit set.
DPB bit toggles.
BCAST bit reset.
DBAC bit set.
DPB bit toggles.
BCAST bit reset.
Bits Updated in Data
Buffer Msg Info Word
No Message Info Word
is written
No Message Info Word
is written
No Message Info Word
is written
MERR bit set.
BUSID bit updated.
Normal CS update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit updated.
(Other error bits reset).
ILCMD bit set.
BUSID bit updated.
MERR bit set.
RTRT bit updated.
(Other error bits reset).
Normal update:
BUSID bit updated.
MERR bit reset.
ILCMD bit reset.
RTRT bit updated.
(Other error bits reset).
Interrupt
Options
None
None
RTAPF
(not
optional)
IWA
IBR
(IXEQZ)
IWA
IBR
(IXEQZ)
ILCMD
IWA
IWA
IBR
(IXEQZ)