hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 36

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

HI-6130, HI-6131
The BC, RT and MT register triplets are described in the respective data sheet sections dedicated to each of those
terminal functions. This data sheet section describes the Hardware Interrupt register triplet, shared by all terminal
modes.
Each individual bit in all three Hardware Interrupt registers is mapped to the same interrupt-causing event when the
corresponding interrupt condition is enabled. Numerous hardware interrupt options are available. At initialization, bits
must be set in the Hardware Interrupt Enable register to identify which interrupt-causing events are heeded by the HI-
613x. Some hardware interrupts (identified later) are automatically enabled after MR master reset. When applications
use just a subset of available interrupt options, selected hardware interrupts are ignored when their corresponding bits
are reset in the Hardware Interrupt Enable Register. Setting an Interrupt Enable register bit from 0 to 1 does not trigger
interrupt recognition for events that occurred while the bit was zero.
Whenever an enabled hardware interrupt event occurs, the Interrupt Log Buffer is updated and a bit is set in the
Hardware Pending Interrupt Register. This action takes place only when the corresponding bit is already set in the
Hardware Interrupt Enable Register when the interrupt event occurs. The host can poll Pending Interrupt Registers
to detect interrupt occurrence, indicated by non-zero value. When the host reads a pending interrupt register, it
automatically clears to 0x0000.
When an enabled hardware interrupt event occurs and the corresponding bit is also set in the Hardware Interrupt Output
Enable Register, the IRQ output pin is asserted. Thus, the Hardware Interrupt Output Enable Register establishes two
interrupt priority levels: high priority hardware interrupts generate an IRQ signal output, while low priority hardware
interrupts do not. The host identifies low priority hardware interrupts by polling the Hardware Pending Interrupt Register.
A single IRQ host interrupt output signal is shared by all enabled interrupt conditions having bits set in the respective
Interrupt Output Enable registers. Since one MIL-STD-1553 message can contain multiple interrupt-causing events,
each IRQ output assertion can result from a single interrupt condition or a combination of interrupt conditions.
When the host receives an IRQ signal from the device, it must identify the event (or events) that triggered the interrupt.
A hardware-assisted interrupt-decoding scheme simplifies interrupt identification. This scheme uses the three low
order bits in the Hardware Pending Interrupt Register.
Upon IRQ interrupt assertion, the host should first read the Hardware Pending Interrupt Register. Bits 15-3 in this
register identify hardware interrupt conditions. The three low-order bits the Hardware Pending Interrupt Register
indicate zero vs. non-zero status for the RT, MT and BC Pending Interrupt Registers. If any of these bits is logic 1, the
corresponding Pending Interrupt Register has one or more interrupt flags set. Any combination of these 3 bits may be
set. Each of the four Pending Interrupt registers self-resets to 0x0000 after the host reads its value. Thus, the host
should retain the value read from the Hardware Pending Interrupt Register when 2 or more bits are non-zero in the bit
2-0 range.
When polling the Pending Interrupt registers to identify low priority interrupts that do not assert the IRQ output, the
same method can be applied. At a single read of the Hardware Pending Interrupt Register reveals zero / non-zero
status of all four Pending Interrupt registers.
To help the host process interrupts, the HI-613x device maintains information from the 32 most recent interrupts in a
64-word ring buffer in RAM, located at the fixed address range 0x0180 to 0x01BF. Each interrupt stores two information
words: the Interrupt Identification Word (IIW) identifies the interrupt type(s) that occurred; the Interrupt Address Word
(IAW) identifies the interrupt source. For interrupts that result from message processing, the IAW contains the 16-bit
address of the command’s Control Word in the Descriptor Table. For hardware interrupts, the IAW value is 0x0000.
The 13th interrupt management register is the Interrupt Count & Log Address Register.
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