hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 144

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
3 − 2
7
6
5
4
Mnemonic
SMCP
TRXDB
ALTBITW
AUTOBSD
MC17OP1:0 R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
HOLT INTEGRATED CIRCUITS
Function
IMT Extended Message Flag Enable.
When register bit 2 equals 0, the recorded status/error flags are limited
to the defined bits in the IRIG-106 Block Status Word. See Section 14.6.
When register bit 2 equals 1, expanded status/error flags are enabled,
occupying “reserved” bit positions in the IRIG-106 Block Status Word.
IMT Checksum Enable
This IMT setting is only meaningful when IMTHTD (register bit 3) equals
0, enabling automatic generation of IRIG-106 data packet header and
packet trailer.
When register bit 1 equals 1, a 16-bit checksum is tallied for the data
packet body, and stored in the packet trailer at packet finalization.
When register bit 1 equals 0, no checksum is tallied for the data packet
body.
Select Simple Monitor Terminal (SMT) or IRIG-106 Monitor Terminal
(IMT).
This register bit must equal logic 0 for IMT operation. When this bit is
zero, the bus monitor operates in IMT IRIG-106 mode with 48-bit time
tag counter resolution.
Automatic Bus Shutdown Enable.
This bit affects bus shutdown and shutdown override for mode code
commands MC20 and MC21.
When the AUTOBSD bit is logic 0, the host is responsible for
implementing “bus shutdown” when mode code command MC20 is
received, as well as implementing “bus shutdown override” when mode
code command MC21 is received.
See the Master Configuration Register BSDTXO bit for other
considerations.
MC17 Sync Option Bits 1:0
If register bits 3-2 equal 11, the data word received with a valid
“synchronize” mode command (MC17) is unconditionally loaded into
the Time-Tag counter, at address 0x0047 for RT1 or 0x0049 for RT2.
For non-broadcast MC17 commands, the counter load occurs before
status word transmission. If register bits 3-2 equal 00, the external host
assumes responsibility for actions needed to perform “synchronize”
duties upon reception of the valid MC17 “synchronize” mode code
command, but status transmission automatically occurs.
The binary 01 and 10 combinations of register bits 3-2 support certain
extended subaddress schemes. If bits 3-2 equal 01, the received data
word is automatically loaded into the Time-Tag counter if bit 0 of the
received data word equals 0. The counter resides at address 0x0047
for RT1 or 0x0049 for RT2. If bits 3-2 equal 10, the received data word
is automatically loaded into the Time-Tag counter if bit 0 of the received
data word equals 1. For non-broadcast MC17 commands, the counter
load occurs before status word transmission.
HI-6130, HI-6131
144