hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 11

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

HI-6130, HI-6131
List of Figures
Figure 1. HI-6130 / HI-6131 Block Diagram................................................................................. 14
Figure 2. Address Mapping for Registers and RAM .................................................................... 21
Figure 3. Bus Controller Message Sequence Structures............................................................. 50
Figure 4. Bus Controller Flag Operation ...................................................................................... 60
Figure 5. Structure of Bus Controller Message Control / Status Blocks in RAM ......................... 62
Figure 6. Simple Monitor Terminal (SMT) Data Storage .............................................................. 95
Figure 7. Deriving the Monitor Filter Table Address from the Received Command Word ........... 99
Figure 8. IRIG-106 Data Packet and Message Storage Summary .............................................113
Figure 9. Deriving the Monitor Filter Table Address from the Received Command Word ......... 121
Figure 10. IRIG-106 Data Fields and Message Storage............................................................ 122
Figure 11. MIL-STD-1553 Command Word Structure ............................................................... 158
Figure 12. Deriving the Illegalization Table Address From the Received Command Word ....... 161
Figure 13. Fixed Address Mapping for Illegalization Table ....................................................... 163
Figure 14. Summary of Illegalization Table Addresses for Mode Code Commands .................. 164
Figure 15. Fixed Address Mapping for Interrupt Log Buffer ...................................................... 167
Figure 16. Address Mapping for Descriptor Table ..................................................................... 169
Figure 17. Deriving a Descriptor Table Control Word Address From Command Word ............. 170
Figure 18. Illustration of Ping-Pong Buffer Mode ...................................................................... 192
Figure 19. Ping-Pong Buffer Mode Example for a Receive Subaddress .................................. 194
Figure 20. Illustration of Indexed Buffer Mode .......................................................................... 197
Figure 21. Indexed Buffer Mode Example for a Receive Subaddress (broadcast disabled) .... 198
Figure 22. Illustration of Circular Buffer Mode 1 ........................................................................ 201
Figure 23. Circular Buffer Mode 1 Example for a Receive Subaddress ................................... 202
Figure 24. Illustration of Circular Buffer Mode 2 ........................................................................ 206
Figure 25. Circular Buffer Mode 2 Example for a Receive Subaddress ................................... 207
HOLT INTEGRATED CIRCUITS
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