hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 34

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
10
11
9
8
7
6
5
4
Mnemonic
RT2RESET
RT1RESET
BCMIP
BCACTIVE
MTMIP
MTPIP
RT2MIP
RT1MIP
R/W
R/W
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
HOLT INTEGRATED CIRCUITS
Function
Remote Terminal 2 Reset.
When written to logic 1, this bit initiates RT2 reset by clearing the STEX
Start Execution bit in the RT2 Configuration Register, then performing
the RT soft reset actions described in the section entitled, “Reset and
Initialization”. This bit remains high until reset is complete. While this
bit remains high, the READY output pin and register bit 15 are held
low, host RAM and register access is suspended. While READY = 0,
any host read access returns the value in this register, regardless of
address provided. Upon reset completion, this bit self-clears to logic 0,
the READY pin goes high and host read/write access is restored.
Remote Terminal 1 Reset.
When written to logic 1, this bit initiates RT1 reset by clearing the STEX
Start Execution bit in the RT1 Configuration Register, then performing
the RT soft reset actions described in the section entitled, “Reset and
Initialization”. This bit remains high until reset is complete. While this
bit remains high, the READY output pin and register bit 15 are held
low, host RAM and register access is suspended. While READY = 0,
any host read access returns the value in this register, regardless of
address provided. Upon reset completion, this bit self-clears to logic 0,
the READY pin goes high and host read/write access is restored.
BC Message in Process.
This bit is high when the BC is processing a MIL-STD-1553 message.
Falling edge occurs at message completion, after register and RAM
buffer updates.
BC Active.
This bit is high when the BC is enabled and running. It will read logic
1 during MIL-STD-1553 message processing and during programmed
delays.
Bus Monitor Message in Process.
This bit is set when a valid MIL-STD-1553 command is decoded, and is
reset upon monitored message completion.
Bus Monitor Packet in Process.
This bit is set at start of a data packet and is reset when the packet is
deemed complete.
Remote Terminal 2 Message in Process.
This bit is set when a valid MIL-STD-1553 command is decoded for
RT2, and is reset upon message completion.
Remote Terminal 1 Message in Process.
This bit is set when a valid MIL-STD-1553 command is decoded for
RT1, and is reset upon message completion.
HI-6130, HI-6131
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