hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 19

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Pin
CE
D15:0
A14:1
A0 / LB
BWID
BTYPE
R/W / WE
STR / OE
WPOL
Function
Input
50KΩ pull-up
In / Out
50KΩ pull-down
Input
50KΩ pull-up
Input
50KΩ pull-up
Input
50KΩ pull-up
Input
50KΩ pull-up
Input
50KΩ pull-up
Input
50KΩ pull-up
Table 2. Pins that apply to HI-6130 only (Host parallel bus interface)
Description
Chip Enable, active low. When asserted, this pin enables host read or write
accesses to device RAM or registers using the host’s parallel bus interface. This
pin is normally connected to a Chip Select output from the host’s bus interface.
Tri-state data bus for host read/write operations upon registers and shared
RAM. All bus read/write operations transact 16 bit words, but bus width can be
configured for 8 or 16 bits. For 8-bit bus width, pins D15:8 are not connected.
Sixteen-bit words are transacted over an 8-bit bus as a pair of byte operations,
with data presented sequentially on pins D7:0. For compatibility with different
host processors when 8-bit bus width is enabled, the BENDI input determines
whether the low order byte is transferred before the high order byte, or vice
versa.
Address bus for host read/write operations upon registers and shared RAM.
When using 16-bit bus width, address bit A0 / (LB) from the host is not used. For
8-bit bus width, output A0 equals 0 during the first byte read/write access; and
equals 1 during the second byte access.
Configuration pin for host bus width. High selects 16-bit bus width, low selects
8-bit bus width.
Configuration pin for host bus read/write control signal style. High selects “Intel
style” using separate read strobe OE (output enable) and write strobe WE. Low
selects “Motorola style” using single active-low read/write strobe STR and read/
write select signal, R/W.
Read/write direction signal R/W when BTYPE pin is low.
Active-low Write Enable WE when BTYPE pin is high.
Used for host read or write accesses to device RAM or registers. This pin or the
CE pin should be high during all address transitions.
Active-low common read/write strobe STR when BTYPE pin is low.
Active-low Output Enable OE when BTYPE pin is high.
Used for host read or write accesses to device RAM or registers.
Configuration pin for WAIT output polarity. When the WPOL pin is low, the “wait”
output is active low (WAIT). When WPOL is high, the “wait” output is active high
(WAIT).
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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