hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 40

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
13
12
10
11
Mnemonic
RAMIF
UNCRE
LBFA
LBFB
MTTTRO
R/W
R/W
R/W
R/W
Reset
1
0
0
HOLT INTEGRATED CIRCUITS
Function
RAM Initialization Fail Interrupt.
This function only applies when the RAMEDC input pin is logic 0 and
the AUTOEN input pin is logic 1 at rising edge of MR Master Reset. This
enables auto-initialization from serial EEPROM, as well as RT or MT soft
reset with auto-initialization. This bit is logic 1 in the Hardware Interrupt
Enable Register and in the Hardware Interrupt Output Enable Register
after MR master reset.
The RAMIF bit is set in the Hardware Pending Interrupt Register (as well
as bit 0 in the Master Status and Reset Register, 0x0001) when one or
more initialized RAM locations do not match their two corresponding
serial EEPROM byte locations. Such failure occurs during auto
initialization, or execution of a partial reset caused by assertion of the
RT1RESET, RT2RESET or MTRESET bits in the Master Status and
Reset Register, 0x0001.
Register bit 14 has a secondary function when input pin RAMEDC is
connected to logic 1. When the RAMEDC pin is high, the available
RAM address space is reduced from 32K words to 24K words, but error
detection and correction (EDC) is performed after every RAM address
read cycle.
Uncorrected 24K RAM Error.
This function only applies when the device RAMEDC input pin is
connected high, configuring the device for 24K RAM with EDC enabled.
The device automatically corrects single-bit errors, but multiple-bit errors
are not correctable.
When an uncorrectable RAM data error is detected, register bit 13 is set
to logic 1. The RAMIF bit 1 in register 0x0001 is also cleared.
When bit 13 is asserted in the Hardware Pending Interrupt Register
0x0009, the host can distinguish a RAMIF interrupt from a UNCRE
interrupt by reading the Master Status and Reset Register 0x0001.
RAMIF bit 1 in that register will be logic 1 for RAMIF interrupt, logic 0 for
UNCRE interrupt.
Loopback Fail Bus A Interrupt (LBFA)
Loopback Fail Bus B Interrupt (LBFB)
For all transmitted words, the device checks MIL-STD-1553 word validity
for the subsequently received/decoded word detected on the bus. This
includes sync, encoding, bit count and parity checking. The last word
in each message transmitted by the device is also checked for data
matching.
The LBFA bit is set each time loop-back detects an invalid or
mismatched word on Bus A. The LBFB bit is set each time loop-back
detects an invalid or mismatched word on Bus B.
MT Time Tag Counter Rollover.
The Bus Monitor time tag counter rolled over from full count to zero.
Depending on options selected in the Time Tag Configuration Register,
the MT time count may be either 16 or 48 bits.
HI-6130, HI-6131
40