hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 111

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

HI-6130, HI-6131
14. IRIG-106 MONITOR TERMINAL (IMT)
The HI-613x can operate as an autonomous MIL-STD-1553 Bus Monitor, requiring minimal host support. Two
fundamentally different monitor modes are offered. Each of these modes has a separate data sheet section describing
registers used and operational details. Information regarding the alternative Simple Monitor Terminal (SMT) may be
found in Section 12.
14.1. Overview
IRIG-106 Monitor Terminal (IMT) mode complies with IRIG-106, a comprehensive standard ensuring interoperability of
aeronautical telemetry at United States Military RCC member ranges. The telemetry group of the Range Commanders
Council maintains the IRIG-106 standard. Chapter 10 of the standard defines operation and interfaces for digital flight
data recorders over a range of telemetry protocols, including MIL-STD-1553. Further information on the IRIG-106
standard can be found at http://irig106.org/
The HI-613x is configured for IMT operation when bit 0 in the MT Configuration Register 0x0029 is logic 0. The IMT
always operates with 48-bit Time Tag resolution. In register 0x0000, MTENA bit 8 is logically ANDed with the MTENA
input pin to enable the Bus Monitor. If the MTENA input pin or register bit equals logic 0, Bus Monitor operation is
disabled. When the pin and MTENA register bit are both logic 1, the Bus Monitor is enabled. Operation commences
when the receiver first decodes MIL-STD-1553 activity meeting the “start record” criteria selected by bits 6-5 in the
MT Configuration Register. If monitor operation is underway when the MTENA register bit or input pin becomes logic
0, monitor operation stops and the open data packet is finalized after completion of any message already underway.
The Holt IRIG-106 Monitor Terminal (hereafter called IMT) uses a single storage stack in device RAM. Recorded
message data, message results and characteristics are stored in multiple-message “data packets”. As they occur,
MIL-STD-1553 messages are appended to the end of the open data packet and time stamped with a 48-bit Time Tag
value. By default, the IMT records all MIL-STD-1553 messages, although it optionally records just selected messages,
based on RT address, subaddress and transmit/receive status for each detected Command Word.
The IMT optionally generates a Packet Header and Packet Trailer consistent with IRIG-106 Chapter 10 specifications.
The header contains various data including data packet size, time stamp and header checksum. The trailer is primarily
comprised of a data checksum. While the IRIG-106 standard requires a header and trailer on each data packet, some
applications will require data packet size exceeding the RAM capacity of the HI-613x device. In this case, the IMT
may be configured to disable automatic header and trailer generation, so the entire RAM buffer is used for message
storage. Upon receiving each end-of-packet interrupt, the host offloads the entire block of new message data, which
may be appended to a large packet buffer RAM, accessible to the host microcontroller. At the appropriate time, the
host then generates the required IRIG-106 packet header and packet trailer.
The IMT can be configured to automatically start a new data packet after finalization of each completed data packet,
or the host microcontroller can command the start of the new data packet. In either case, the starting address for the
new packet follows the last storage address of the previous packet (even when the last packet was finalized due to
imminent buffer overrun). The device stores packet data in circular buffer fashion, automatically wrapping around to
the buffer start address after the last buffer address is written. The host microcontroller is responsible for offloading
each data packet in a timely manner to avoid data overwrite by the HI-613x device. One strategy: enable a “packet
ready” interrupt, as well as an “N-word warning before full buffer” interrupt triggered halfway through the IMT RAM
buffer capacity. The host microcontroller uses these alternating interrupts to pace data buffer offloading, reading a half
buffer each time one of the two interrupts occurs.
The HI-613x IMT is highly flexible. According to the IRIG-106 standard, the Block Status Word stored for each MIL-
STD-1553 message contains several reserved status bits which always read logic 0. The HI-613x device optionally
uses these bits to convey additional status information to the host; the host then resets the reserved bits before
including the Block Status Word in the IRIG-106 data packet.
HOLT INTEGRATED CIRCUITS
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