hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 29

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

9. REGISTERS USED BY ALL DEVICE FUNCTIONS
9.1.
All bits in this 16-bit register are read-write and are fully maintained by the host. This register is cleared after MR pin
master reset, and is unaffected by assertion of the MTRESET, RT1RESET or RT2RESET bits in the Master Status
and Reset Register (0x0001).
15 14 13 12 11 10
Bit No.
0
15
14
13
12
0
Master Configuration Register (0x0000)
0
Mnemonic
TXINHA
TXINHB
BCSTRT
BCENA
0
0
0
0
9
0
8
RW
R/W
R/W
R/W
R/W
R/W
7
0
0
6
Reset
0
5
0
0
0
0
4
0
0
3
Function
Transmit Inhibit Bus A.
This bit is logically ORed with the TXINHA input pin. This register bit and
the corresponding TXINHA pin globally affect all enabled 1553 devices
(BC, MT, RT). This inhibit disables all transmission on Bus A.
Transmit Inhibit Bus B.
This bit is logically ORed with the TXINHB input pin. This register bit and
the corresponding TXINHB pin globally affect all enabled 1553 devices
(BC, MT, RT). This inhibit disables all transmission on Bus B.
Bus Controller Start.
If the BCENA input pin and BCENA register bit are both logic 1, a host
write which sets this bit to 1 begins Bus Controller operation. When
written to 1, this bit self-resets to 0. This bit always reads back at logic 0
state.
Bus Controller Enable.
This bit is logically ANDed with the BCENA input pin. If either the input
pin or this register bit is logic 0, Bus Controller operation is disabled. The
BCENA input pin should be connected to ground in applications not using
BC mode. This bit cannot be set if BCENA input pin = 0.
When the BCENA pin and BCENA register bit are both logic 1, the Bus
Controller device is enabled, but BC operation does not begin until
BCSTRT bit 13 is set. If this register bit or the BCENA input pin becomes
logic 0 while BC operation is underway, BC operation is immediately
terminated without waiting for message completion.
HOLT INTEGRATED CIRCUITS
0
2
HI-6130, HI-6131
0
1
0
0
MR Reset
Host Access
Bit
29