hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 109

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011)
13.14.2. SMT Bus Monitor Pending Interrupt Register (0x0008)
13.14.3. SMT Bus Monitor Interrupt Output Enable Register (0x0015)
Three registers govern SMT interrupt behavior: the SMT Interrupt Enable Register, the SMT Pending Interrupt Register
and the SMT Interrupt Output Enable Register. When a bit is set in the SMT Interrupt Enable Register, the corresponding
SMT interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally
disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the
bit was zero.
When an enabled SMT interrupt event occurs, the corresponding bit is set in the SMT Pending Interrupt Register
and the Interrupt Log Buffer is updated. To simplify interrupt decoding, MTIP bit 1 in the Hardware Pending Interrupt
Register is also set whenever one or more bits are set in the SMT Pending Interrupt Register.
If the corresponding bit is already set in the SMT Interrupt Output Enable Register, the nIRQ output pin is asserted at
Pending Interrupt Register assertion. The SMT Interrupt Output Enable Register establishes two priority levels: high
priority interrupts generate an IRQ output while low priority interrupts do not. Both priority levels update the SMT
Pending Interrupt Register and the Interrupt Log Buffer. The host detects low priority (masked) interrupts by polling
SMT Pending Interrupt Register.
The table below describes the bit descriptions shared by all three SMT interrupt registers.
15
15
15
0
0
0
14 13 12 11 10 9
14 13 12 11 10 9
14 13 12 11 10 9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
0
0
0
8
8
8
0
0
0
R
7
7
7
0
0
0
6
6
6
0
0
0
0
5
0
5
0
5
4
4
4
0
0
0
3
3
3
0
0
0
HOLT INTEGRATED CIRCUITS
0
2
0
2
0
2
HI-6130, HI-6131
R
R
1
1
1
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
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