hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 192

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Message processing alternates between Data Buffers A and B. Upon sucessful message completion, the DPB
bit in Descriptor Control Word is updated so next message uses other buffer. Buffers are overwritten every
other message.
Separate buffer for broadcast messages is optional. There is no alternate buffer for successive
broadcast messages.
Memory Address for the Applicable
Subaddress Block is Derived From
the Decoded Command Word
Increasing
(if NOTICE2 is asserted)
Memory
Address
Broadcast Message
Figure 18. Illustration of Ping-Pong Buffer Mode
HOLT INTEGRATED CIRCUITS
Message Info Word
B’cast Data Pointer
Descriptor Block
Data Words 2-31
for Subaddress
HI-6130, HI-6131
Time-Tag Word
for Broadcast
Buffer Space
Data Pointer A
Data Word 32
Data Pointer B
Subaddress
Control Word
Data Word 1
(optional)
192
Message #2
Message #4
Message #6
Message #1
Message #3
Message #5
etc.
etc.
Message Info Word
Message Info Word
Data Words 2-31
Data Words 2-31
Time-Tag Word
Time-Tag Word
Data Word 32
Data Word 32
Data Buffer B
Data Buffer B
Data Word 1
Subaddress
Data Word 1
Subaddress
Assigned
Assigned