hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 205

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

For receive subaddresses using Circular Buffer Mode
2,
circular data buffer. The first data word received for
each message is stored at the location indicated by
the CA pointer.
received (as specified in the command word) the device
writes Message Information and Time-Tag words in
the Message Information Buffer then updates the
descriptor CA Current Address and MIBA Message
Information pointers for next-message readiness. If the
predetermined total number of messages has not yet
been transacted, MIBA points to the next location in the
message information buffer and CA points to the next
location in the data buffer. If the completed message
is the last message in the block, the CA current (data)
address and MIBA message Information pointers are
reinitialized to their base address values.
Word bits 7:4 tell the device how many MIBA lower bits
to reset.) If the descriptor Control Word IXEQZ bit is
asserted (and if the Interrupt Enable Register IXEQZ bit
is asserted) the device generates a Buffer Full / Empty
interrupt, asserting the INTMES interrupt output.
For transmit subaddresses using Circular Buffer Mode
2, the device transmits data from the assigned RAM buf-
fer, starting at the location specified by the CA pointer.
The first data word transmitted is stored at the loca-
tion specified by the CA pointer. After all data words
are transmitted (as specified in the command word)
the device writes Message Information and Time-Tag
words in the Message Information Buffer then updates
the descriptor CA Current Address and MIBA Message
Information pointers for next-message readiness. If the
predetermined total number of messages has not yet
been transacted, MIBA points to the next location in the
message information buffer and CA points to the next lo-
cation in the data buffer. If the completed message is the
last message in the block, the CA current (data) address
and MIBA message Information pointers are reinitialized
to their base address values. (Control Word bits 7:4 tell
the device how many MIBA lower bits to reset.) If the
descriptor Control Word IXEQZ bit is asserted (and if
the Interrupt Enable Register IXEQZ bit is asserted) the
device generates a Buffer Full / Empty interrupt, assert-
ing the INTMES interrupt output.
Circular Buffer Mode 2 does not support NOTICE2 seg-
regation of broadcast data, even when the NOTICE2 bit
equals 1 in Configuration Register 1. Data words from
broadcast receive commands are stored in the same
buffer with data from non-broadcast receive commands.
The BCAST bit in the Message Information Word reflects
broadcast or non-broadcast status for each stored mes-
sage. If broadcast messages to the subaddresss are not
expected during data block transmission or will result in
data block error, the host can illegalize broadcast com-
the device stores received data words in the
After the correct number of words is
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
(Control
205
mands for the subaddress, either permanently or only
when block transmission is scheduled.
For transmit subaddresses using Circular Buffer Mode 2,
occurrences of broadcast-transmit commands to RT31
do not result in bus transmission. However these mes-
sages update the Message Information Word addressed
by the Message information Block (MIB) pointer (and the
following Time-Tag Word) but afterwards, the MIB and
CA pointers remain unchanged. The next transmit com-
mand to the same subaddress, whether broadcast or
not, overwrites the Message Information and Time-Tag
Word locations written by the previous broadcast trans-
mit command.