hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 153

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

The device automatically resets the Time-Tag Counter when a “synchronize” mode command without data (MC1) is
received. In addition, the host can reset, load or capture the Time Tag count at any time by asserting action bits in
the Time Tag Configuration Register. Load and capture operations utilize the RT Time Tag Utility Registers, described
below.
The MC17OP1:0 bits in the Remote Terminal Configuration Registers allow automatic loading of Time-Tag count using
the data word received with a “synchronize with data” mode command, MC17. If both of these bits equal one, the data
word received with a valid “synchronize” mode command (MC17) is unconditionally loaded into the Time-Tag counter.
For non-broadcast MC17 commands, the counter load occurs before status word transmission. If both MC17OP1 and
MC17OP0 bits equal 0, the external host assumes responsibility for actions needed to perform “synchronize” duties
upon reception of the valid MC17 “synchronize” command, but status transmission occurs automatically.
The binary 01 and 10 combinations of these bits support certain extended subaddressing schemes. If the MC17OP1:0
bits equal 01, the received data word is automatically loaded into the Time-Tag counter if the low order bit of the re-
ceived data word (bit 0) equals 0. If the MC17OP1:0 bits equal 10, the received data word is automatically loaded into
the Time-Tag counter if the low order bit of the received data word (bit 0) equals 1. For non-broadcast MC17 com-
mands, the counter is loaded before status word transmission.
18.13. Remote Terminal 1 (RT1) Time Tag Utility Register (0x004A)
These 16-bit registers are Read-Write and are fully maintained by the host. These registers are cleared after MR pin
master reset, but are not affected by assertion of RTxRESET remote terminal software reset in the Master Status and
Reset Register (0x0001). These registers have two functions associated with the two free-running Remote Terminal
Time Tag Counters:
18.13.1. RT Time Tag Counter Loading
When the RT1TTA1-0 bits 9-8 in Time Tag Counter Configuration Register 0x0039 are written to 1-0, the value con-
tained in the RT1 Time Tag Utility Register (0x0048) is loaded into the RT1 Time Tag Counter (0x0047).
When the RT2TTA1-0 bits 11-10 in Time Tag Counter Configuration Register 0x0039 are written to 1-0, the value
contained in the RT2 Time Tag Utility Register (0x0049) is loaded into the RT2 Time Tag Counter (0x004A).
18.13.2. RT Time Tag Count Match Interrupts
If the RT1TTM or RT2TTM interrupts are enabled in the Hardware Interrupt Enable Register (0x000F), then time tag
“count match” interrupts are enabled. When enabled for RT1, the hardware RT1TTM interrupt occurs when the free
running RT1 Time Tag Counter (0x0047) matches the value contained in the RT1 Time Tag Utility Register (0x0048).
When enabled for RT2, the hardware RT2TTM interrupt occurs when the free running RT2 Time Tag Counter (0x0049)
matches the value contained in the RT2 Time Tag Utility Register (0x004A).
MSB
15 14 13 12 11 10
0
0
Remote Terminal 2 (RT2) Time Tag Utility Register (0x004C)
0
0
0
0
Register Value
0
9
0
8
RW
7
0
0
6
0
5
4
0
0
3
HOLT INTEGRATED CIRCUITS
0
2
HI-6130, HI-6131
0
1
LSB
0
0
MR Reset
Host Access
Bit
153