hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 81

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

11.4. Bus Controller (BC) Frame Time Remaining Register (0x0035)
This 16-bit register is Read-Write. A value is written to this register upon execution of the BC instruction list op code,
“Load Frame Timer” (LFT). Time remaining value begins decrementing upon execution of the Start Frame Timer (SFT)
instruction op code. The parameter word accompanying the op code word is the desired time value, expressed with a
resolution of 100 µs per LSB, with a maximum value of 6.5535 sec.
11.5. Bus Controller (BC) Time To Next Message Register (0x0036)
This 16-bit register is Read-Only. This programmable time-to-next message timer is loaded on a message-by-mes-
sage basis, with values from word 4 in each Message Control / Status Block. The BC time-to-next message is defined
as the time from the start of the current message to the start of the next message, i.e., mid-sync zero crossing to the
next mid-sync zero crossing. This timer provides a 1 µs per LSB resolution, with a maximum value of 65.535 ms.
11.6. Bus Controller (BC) Condition Code Register (Read 0x0037)
Sharing the same register address as the Write-Only General Purpose Flag Register, this 16-bit register is Read-Only.
Bit 15 indicates BC run/stop status. With this exception, the upper 8 bits indicate results from the last message pro-
cessed by the Bus Controller. The lower 8 bits of this register are general purpose flag bits, which may be set, cleared,
or toggled by the host using the BC General Purpose Flag Register (see page 33), or by the device by means of the
General Purpose Flag Bits (FLG) instruction op code. Further, bits 1-0 can be set or cleared by the device BC logic
by execution of two BC instruction op codes: Compare to Frame Timer (CFT) and Compare to Message Timer (CMT).
MSB
MSB
15 14 13 12 11 10 9
0
15 14 13 12 11 10
15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Value
Register Value
0
9
0
9
0
8
0
8
0
8
RW
R
R
0
7
7
7
0
0
0
6
0
6
0
6
0
5
0
0
5
5
0
4
4
4
0
0
0
3
0
3
0
3
HOLT INTEGRATED CIRCUITS
0
2
0
0
2
2
HI-6130, HI-6131
0
1
0
1
0
1
LSB
LSB
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
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