hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 223

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Multiple bytes may be transferred when the host holds
CE low after the first byte transferred, and continues to
clock SCK in multiples of 8 clocks. A rising edge on CE
chip enable terminates the serial transfer and reinitial-
izes the HI-6131 SPI for the next transfer. If CE goes
high before a full byte is clocked by SCK, the incomplete
byte clocked into the device SI pin is discarded.
Two byte transfers are needed for SPI exchange of 16-
bit register values or RAM data. “Big endian” byte order
is used for SPI data transfers. The high order byte (bits
15:8) is transferred before the low order byte (bits 7:0).
In the general case, both master and slave simulta-
neously send and receive serial data (full duplex) per
Figure 26. However the HI-6131 operates half duplex,
maintaining high impedance on the SO output, except
when actually transmitting serial data. When the HI-
6131 is sending data on SO during read operations, ac-
tivity on its SI input is ignored. Figure 27 and Figure 28
show actual behavior for the HI-6131 SO output.
24.2.2. HI-6131 SPI Commands
For the HI-6131, each SPI read or write operation be-
gins with an 8-bit command byte transferred from the
host to the device after assertion of CE. Since HI-6131
command byte reception is half-duplex, the host dis-
cards the dummy byte it receives while serially transmit-
ting the command byte.
The HI-6131 SPI command set uses the most significant
command bit to specify whether the command is Read
or Write. The command byte MSB is zero for read com-
mands, and one for write commands.
24.2.3. Fast-Access Commands for Registers
The SPI command set includes directly-addressed read
commands for registers 0 through 15. The 8-bit pattern
for these read commands has the general form
where RRRR is the 4-bit register address. These fast-
access read commands appear in Table 23.
24.2.4. Fast-Access Write Commands for
The SPI command set includes directly-addressed write
commands for registers 0 through 63. The 8-bit pattern
for these read commands has the general form
0-15
Registers 0-63
1-0-R-R-R-R-R-R
0-0-R-R-R-R-0-0
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
223
where RRRRRR is the 6-bit register address. The fast-
access write commands appear in Table 23.
Figure 27 and Figure 28 show read and write timing as
it appears for fast-access register operations. The com-
mand byte is immediately followed by two data bytes
comprising the 16-bit data word read or written. For a
register read or write, CE is negated after the 2-byte
data word is transferred.
24.2.5. Indirect Addressing of RAM and
Refer to the HI-6131 SPI command set shown in Table
24. All SPI commands other than fast-access use a
Memory Address Pointer register to indicate the start-
ing address for read or write transactions. Four “Memory
Address Pointers” reside at register addresses 0x000B
through 0x000E. Just one Memory Address Pointer
(MAP) is active (enabled) at any time.
The active Memory Address Pointer is selected by
writing the MAPSEL bits 11-10 in the Master Configu-
ration Register. Or use the SPI instruction op codes
0xD8, 0xD9, 0xDA or 0xDB which enable MAP registers
0x000B, 0x000C, 0x000D or 0x000E respectively, by
automatically writing MAPSEL bits 11-10 in the Master
Configuration Register.
The active Memory Address Pointer must be initialized
before any read or write operation, other than fast-ac-
cess.
To write the active MAP register, use a fast-access write
op code, followed by the desired 16-bit memory address:
To read the active MAP register, use a fast-access write
op code. The current MAP 16-bit value is clocked out in
the next 16 sequential SCK clock cycles:
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Writing MAP register 0x000B uses SPI op code
0x8B followed by 16-bit address.
Writing MAP register 0x000C uses SPI op code
0x8C followed by 16-bit address
Writing MAP register 0x000D uses SPI op code
0x8D followed by 16-bit address.
Writing MAP register 0x000E uses SPI op code
0x8E followed by 16-bit address.
Reading MAP register 0x000B uses SPI op code
0x2C
Reading MAP register 0x000C uses SPI op code
0x30
Reading MAP register 0x000D uses SPI op code
0x34
Registers