hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 155

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

18.14.1. Remote Terminal (RT) Interrupt Enable Register (0x0012)
18.14.2. Remote Terminal (RT) Pending Interrupt Register (0x0009)
18.14.3. Remote Terminal (RT) Interrupt Output Enable Register (0x0016)
Three registers govern RT interrupt behavior: the RT Interrupt Enable Register, the RT Pending Interrupt Register
and the RT Interrupt Output Enable Register. When a bit is set in the RT Pending Interrupt Enable Register, the
corresponding RT interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is
unconditionally disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that
occurred while the bit was zero.
When an enabled RT interrupt event occurs, the corresponding bit is set in the Pending RT Interrupt Register and the
Interrupt Log Buffer is updated. To simplify interrupt decoding, RTIP bit 2 in the Hardware Pending Interrupt Register
is also set whenever a message sets at least one bit in the RT Pending Interrupt Register.
If the corresponding bit is set in the RT Interrupt Output Enable Register, the IRQ output is asserted at message
completion. The RT Interrupt Output Enable Register establishes two priority levels: high priority interrupts generate an
nIRQ output while low priority interrupts do not. Both priority levels update the Pending Interrupt Register and Interrupt
Log Buffer. The host can detect low priority (masked) interrupts by polling Pending Interrupt registers.
The following table describes the shared bit descriptions used by all three RT interrupt registers.
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
0
0
0
8
8
8
0
0
0
R
7
7
7
0
0
0
6
6
6
0
0
0
0
5
0
5
0
5
4
4
4
0
0
0
3
3
3
0
0
0
HOLT INTEGRATED CIRCUITS
0
2
0
2
0
2
HI-6130, HI-6131
R
1
1
R
1
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
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