hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 88

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010)
11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007)
11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014)
Three registers govern BC interrupt behavior: the BC Interrupt Enable Register, the BC Pending Interrupt Register
and the BC Interrupt Output Enable Register. When a bit is set in the BC Interrupt Enable Register, the correspond-
ing BC interrupt is enabled. When a bit is reset in this register, the corresponding interrupt event is unconditionally
disregarded. Setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the
bit was zero.
When an enabled BC interrupt event occurs, the corresponding bit is set in the BC Pending Interrupt Register and the
Interrupt Log Buffer is updated. To simplify interrupt decoding, BCIP bit 0 in the Hardware Pending Interrupt Register
is also set whenever a message sets at least one bit in the BC Pending Interrupt Register.
If the corresponding bit is set in the BC Interrupt Output Enable Register, the IRQ output is asserted at message
completion. The BC Interrupt Output Enable Register establishes two priority levels: high priority interrupts generate
an nIRQ output while low priority interrupts do not. Both priority levels update the Pending Interrupt Register and Inter-
rupt Log Buffer. The host can detect low priority (masked) interrupts by polling Pending Interrupt registers.
The table below first describes the common bits 15-3 in all three BC interrupt registers and then describes register-
to-register differences for bits 2-0.
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RW
RW
0
0
0
8
R
8
8
0
0
0
7
7
7
0
0
0
6
6
6
0
0
0
0
5
0
5
0
5
4
4
4
0
0
0
3
3
3
0
0
0
HOLT INTEGRATED CIRCUITS
0
2
0
2
0
2
HI-6130, HI-6131
R
1
1
R
1
0
0
0
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
88