HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 89

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Literal Constant: Byte literal constant is placed inside the instruction code as immediate data.
Since the instruction length is fixed to 16 bits, word and longword literal constant is not placed
inside the instruction code, but in a table in memory. The table in memory is referenced with a
MOV instruction using PC-relative addressing mode with displacement.
Absolute Addresses: When data is referenced by absolute address, the absolute address value is
placed in a table in memory beforehand as well as word or longword literal constant. Using the
method whereby immediate data is loaded when an instruction is executed, this value is
transferred to a register and the data is referenced using register indirect addressing mode.
16-Bit/32-Bit Displacement: When data is referenced with a 16- or 32-bit displacement, the
displacement value is placed in a table in memory beforehand. Using the method whereby word or
longword immediate data is loaded when an instruction is executed, this value is transferred to a
register and the data is referenced using indexed register indirect addressing mode.
2.5.2
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3
Addressing
Mode
Register
direct
Register
indirect
Register
indirect with
post-increment
Example:
CPU Instruction Addressing Modes
Addressing Modes and Effective Addresses for CPU Instructions
MOV.W
Instruction
Format
Rn
@Rn
@Rn+
@(disp, PC)
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a
word operand, 4 for a longword operand.
1/2/4
Rn
Rn
Rn + 1/2/4
+
Rn
Rn
Rev. 1.00 Dec. 27, 2005 Page 45 of 932
Calculation
Formula
—
Rn
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 →
Rn
REJ09B0269-0100
Section 2 CPU