HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 174
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 174 of 980
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Section 3 DSP Operating Unit
3. Zero Value Mode: CS[2:0] = 010
4. Overflow Mode: CS[2:0] = 011
5. Signed Greater Than Mode: CS[2:0] = 100
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
• Overflow Protection
Rev. 1.00 Dec. 27, 2005 Page 130 of 1044
REJ09B0269-0100
The DC bit is set when the operation result is a negative value, and cleared when the operation
result is zero or a positive value.
The DC bit is set when the operation result is zero; otherwise it is cleared.
The DC bit is set when an overflow occurs.
The DC bit is always cleared.
The DC bit is always cleared.
The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section
3.5.11, Overflow Protection, for details.
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