HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 643
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
8
7 to 2
1
Bit Name
RXE
—
TXRST
Initial
Value
0
All 0
0
R/W
R/W
R
R/W
Description
Reception Enable
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal). When
the 1 setting for this bit becomes valid, the SIOF begins
the reception of data from the RXD_SIO pin. When
receive data is stored in receive FIFO, the SIOF issues a
reception transfer request according to the setting of the
RFWM bit in SIFCTR. This bit is initialized by a receive
reset.
0: Disables data reception from RXD_SIO
1: Enables data reception from RXD_SIO
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmission Reset
This bit setting becomes valid immediately. When the 1
setting for this bit becomes valid, the SIOF immediately
sets transmit data from the TXD_SIO pin to 1, and
initializes the transmission data register and transmission-
related status register. The following are initialized.
•
•
•
•
As the SIOF is cleared automatically at the completion of
reset operation, this bit is always read as 0.
0: Transmission operation is not reset
1: Resets transmission operation
SITDR
Transmit FIFO write/read pointer
TCRDY, TFEMP, and TDREQ bits in SISTR
TXE bit
Rev. 1.00 Dec. 27, 2005 Page 599 of 932
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100
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