HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 651
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.3.9
SIIER is a used to enable the issue of SIOF interrupts. When each of the bits of this register is set
to 1, and the corresponding bit of the SISTR is set to 1, the SIOF issues an interrupt. SIIER is
initialized by a power-on reset or software reset.
Bit
15
14
13
12
11
10
9
Bit Name
TCRDYE
TFEMPE
TDREQE
RCRDYE
RFFULE
SIOF Interrupt Enable Register (SIIER)
Initial
Value
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should always
be 0.
Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty (control
Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer requests
1: Enables interrupts due to transmit data transfer requests
Reserved
This bit is always read as 0. The write value should always
be 0.
Receive Control Data Ready Enable
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
Receive FIFO Full Enable
0: Disables interrupts due to receive FIFO full
1: Enables interrupts due to receive FIFO full (control
(control interrupt)
interrupt)
(transmit interrupt)
(control interrupt)
interrupt)
Rev. 1.00 Dec. 27, 2005 Page 607 of 932
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100
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