HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 522
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 522 of 980
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Section 13 Direct Memory Access Controller (DMAC)
Table 13.4 Selecting External Request Detection with DL, DS Bits
When DREQ is accepted, the DREQ pin becomes request accept disabled state (non-sensitive
period). After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again
becomes request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is aborted after the same number of transfer has been performed as requests.
Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 13.5 Selecting External Request Detection with DO Bit
On-Chip Peripheral Module Request Mode: In this mode, the transfer is performed in response
to the transfer request signal of an on-chip peripheral module.
The DMA transfer request signals comprise the transmit data empty transfer request and receive
data full transfer request from the SCIF0, SCIF1, SIOF0, and SIOF1 set by DMARS0 to
DMARS2.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal. When a transfer
request is set to TXI of the SCIF0, the transfer destination must be the SCIF0’s transmit data
Rev. 1.00 Dec. 27, 2005 Page 478 of 932
REJ09B0269-0100
DL
0
1
CHCR
DO
0
1
CHCR
DS
0
1
0
1
plus 1) times.
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
External Request
Overrun 0
Overrun 1
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