HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 293
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 293 of 980
- Download datasheet (6Mb)
Note:
8.4.3
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to
IRQ5 individually: rising edge, falling edge, high level, or low level. This register is initialized to
H′4000 by a power-on reset or manual reset, but is not initialized in standby mode.
Bit
7
6
5
4
3
2
1
0
Bit
15
14
*
Interrupt Control Register 1 (ICR1)
Bit Name
Bit Name
MAI
IRQLVL
when NMI input is high, 0 when NMI input is low.
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
1
R/W
R
R
R
R
R
R
R
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
All Interrupt Mask
When this bit is set to 1, all interrupt requests
are masked while low level is input to the NMI
pin. In standby mode, an NMI interrupt is
masked.
0: When the NMI pin is low, all interrupt requests
1: When the NMI pin is low, all interrupt requests
Interrupt Request Level Detection
Enables or disables the use of pins IRQ3 to
IRQ0 as four independent interrupt pins. The
IRQ4 and IRQ5 pins are not affected.
0 : Use of pins IRQ3 to IRQ0 as four
1 : Use of pins IRL3 to IRL0 as encoded 15 level
are not masked
are masked
independent interrupt pins enabled
interrupt pins
Rev. 1.00 Dec. 27, 2005 Page 249 of 932
Section 8 Interrupt Controller (INTC)
REJ09B0269-0100
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