HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 638

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
17.3.3
SITDAR is used to specify the position of the transmit data in a frame (slot number). SITDAR is
initialized by a power-on reset and software reset.
Rev. 1.00 Dec. 27, 2005 Page 594 of 932
REJ09B0269-0100
Bit
2
1
0
Bit
15
14 to 12
11
10
9
8
7
Bit Name
BRDV2
BRDV1
BRDV0
Serial Transmit Data Assign Register (SITDAR)
Bit Name
TDLE

TDLA3
TDLA2
TDLA1
TDLA0
TDRE
Initial
Value R/W
0
0
0
Initial
Value
0
All 0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Baud Rate Generator’s Division Ratio Setting (BRDV)
Set the frequency division ratio BRDV for the output stage
of the baud rate generator. The final frequency division ratio
of the baud rate generator is determined by BRPS × BRDV
(maximum 1/1024).
000: Prescalar output × 1/2
001: Prescalar output × 1/4
010: Prescalar output × 1/8
011: Prescalar output × 1/16
100: Prescalar output × 1/32
Note: Other than above is reserved (setting prohibited).
Description
Transmit Left Channel Data Enable
0: Disables left channel data transmission
1: Enables left channel data transmission
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Left Channel Data Assigns
Specify the position of left-channel data in transmit frame
as B′0000 to B′1110. Transmit data for the left channel is
specified in bits SITDL15 to SITDL0 in SITDR.
Note: If the TDLA3 to TDLA0 bits are set to B′1111,
Transmit Right Channel Data Enable
0: Disables right channel data transmission
1: Enables right channel data transmission
operation is not guaranteed.