HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 88

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
Note: When the external memory is accessed through the E-DMAC module, big endian is
2.5
2.5.1
Instruction Length: All instructions have a fixed length of 16 bits and are executed in the
sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one cycle.
All data items are handles in longword (32 bits). Memory can be accessed in byte, word, or
longword. In this case, Memory byte or word data is sign-extended and operated on as longword
data. Immediate data is sign-extended to longword size for arithmetic operations (MOV, ADD,
and CMP/EQ instructions) or zero-extended to longword size for logical operations (TST, AND,
OR, and XOR instructions).
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly on memory.
Delayed Branching: Unconditional branch instructions are executed as delayed branches. With a
delayed branch instruction, the branch is made after execution of the instruction (called the slot
instruction) immediately following the delayed branch instruction. This minimizes disruption of
the pipeline when a branch is made.
This LSI supports two types of conditional branch instructions: delayed branch instruction or
normal branch instruction.
T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a
conditional branch is performed according to whether the result is True or False. Processing speed
has been improved by keeping the number of instructions that modify the T bit to a minimum.
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REJ09B0269-0100
Example:
Example:
supported, but little endian is not supported. Therefore, if the external memory is accessed
through the E-DMAC module in little endian mode, data format should be converted from
big endian mode to little endian mode through software.
Features of CPU Core Instructions
Instruction Execution Method
BRA
ADD
ADD
CMP/EQ
BT
TARGET
R1, R0
#0, R0 ; The T bit is set to 1 if R0 is 0.
#1, R0 ; The T bit cannot be modified by the ADD instruction
Target ; Branch to TARGET if the T bit is set to 1 (R0=0).
; ADD is executed before branching to the TARGET