HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 521

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.4.2
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. The request mode is selected in the RS3 to RS0 bits in the DMA channel control
registers 0 to 5 (CHCR_0 to CHCR_5), and the DMA extension resource selectors 0 to 2
(DMARS0 to DMARS2).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR_0 to CHCR_5 and the DME bit of
the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_5 AE bit
of DMAOR, and the NMIF bit of DMAOR are all 0.
External Request Mode: In this mode a transfer is performed at the request signals (DREQ0 or
DREQ1) of an external device. Choose one of the modes shown in table 13.3 according to the
application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME =
1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input.
Table 13.3 Selecting External Request Modes with RS Bits
Whether the DREQ is detected by either the edge or level of the signal input is selected with the
DREQ level (DL) bit and DREQ select (DS) bit in CHCR_0 and CHCR_1 as shown in table 13.4.
The source of the transfer request does not have to be the data transfer source or destination.
RS3
0
0
RS2
0
0
DMA Transfer Requests
RS1
0
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Section 13 Direct Memory Access Controller (DMAC)
Any
memory-mapped
external device
External device with
DACK
Source
External memory,
Rev. 1.00 Dec. 27, 2005 Page 477 of 932
Destination
Any
External device with
DACK
External memory,
memory-mapped
external device
REJ09B0269-0100