HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 811

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3.2
When 1 is written to the transmit request bit (TR) in the E-DMAC transmit request register
(EDTRR) while the TE bit in ECMR is set to 1, the E-DMAC reads the descriptor following the
previously used descriptor from the transmit descriptor list (or the descriptor indicated by the
transmit descriptor start address register (TDLAR) at the initial start time). If the TACT bit of the
read descriptor is set to 1 (valid), the E-DMAC sequentially reads transmit frame data from the
transmit buffer start address specified by TD2 for transfer to the EtherC. The EtherC creates a
transmit frame and starts transmission to the MII. After DMA transfer of data equivalent to the
buffer length specified in the descriptor, the following processing is carried out according to the
TFP value.
1. TFP = 00 or 10 (frame continuation):
2. TFP = 01 or 11 (frame end):
As long as the TACT bit of a read descriptor is set to 1 (valid), the reading of E-DMAC
descriptors and the transmission of frames continue. When a descriptor with the TACT bit cleared
to 0 (invalid) is read, the E-DMAC clears the TR bit in EDTRR to 0 and completes transmit
processing.
Descriptor write-back (writing 0 to the TACT bit) is performed after DMA transfer.
Descriptor write-back (writing 0 to the TACT bit and writing status) is performed after
completion of frame transmission.
Transmission
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 1.00 Dec. 27, 2005 Page 767 of 932
REJ09B0269-0100