HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 515
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HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.3.6
DMARS is a 16-bit readable/writable register that specifies the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer requests of the SCIF0, SCIF1, SIOF0, and SIOF1.
When MID and RID other than the values listed in table 13.2 are set, the operation of this LSI is
not guaranteed. The transfer request from DMARS is valid only when bits RS3 to RS0 has been
set to B'1000 in CHCR0 to CHCR5. Otherwise, even if DMARS has been set, a transfer request
source is not accepted.
DMARS is initialized to H'0000 at reset and retains the current value in standby or module
standby mode.
• DMARS0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2)
Bit Name
C1MID5
C1MID4
C1MID3
C1MID2
C1MID1
C1MID0
C1RID1
C1RID0
C0MID5
C0MID4
C0MID3
C0MID2
C0MID1
C0MID0
C0RID1
C0RID0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transfer request module ID for DMA channel 1 (MID)
See table 13.2.
Transfer request register ID for DMA channel 1 (RID)
See table 13.2.
Transfer request module ID for DMA channel 0 (MID)
See table 13.2.
Transfer request register ID for DMA channel 0 (RID)
See table 13.2.
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 471 of 932
REJ09B0269-0100
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