HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 814
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 814 of 980
- Download datasheet (6Mb)
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Reception flowchart
Rev. 1.00 Dec. 27, 2005 Page 770 of 932
REJ09B0269-0100
This LSI + memory
EtherC/E-DMAC
descriptor and
receive buffer
initialization
[Legend]
EtherC/E-DMAC initialization: Executes a software reset with the SWR bit in EDMR set to 1.
Receive descriptor and receive buffer setting: Sets receive descriptors and receive buffers, and sets EtherC and E-DMAC
Start of reception: Occurs when 1 is written to the RE bit in ECMR and the RR bit in EDRRR.
Receive descriptor read: The E-DMAC reads a receive descriptor.
Receive data transfer: Writes receive data from the receive FIFO to the receive buffer by using DMA transfer by the E-DMAC.
Receive descriptor write-back: The E-DMAC writes 0 to the RACT bit and writes the receive status to the receive descriptor.
Receive
setting
Receive descriptor read
Receive descriptor read
(preparation for receiving
the next frame)
Receive data transfer
Receive data transfer
Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor)
Receive descriptor
read
Start of reception
Receive descriptor
write-back
Receive descriptor
write-back
E-DMAC
Reception
completed
registers, then writes 1 to the RE bit in ECMR and the RR bit in EDRRR.
Receive FIFO
EtherC
Frame reception
Ethernet
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