HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 279
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 279 of 980
- Download datasheet (6Mb)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
8.1
The INTC has the following features:
• 16 levels of interrupt priority can be set
• NMI noise canceler function
• IRQ interrupts can be set
• Interrupt request signal can be externally output (IRQOUT pin)
8.1.1
Figure 8.1 shows a block diagram of the INTC.
By setting the interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ
interrupts can be selected from 16 levels for individual request sources.
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as a noise
canceler.
Detection of low level, rising edge, falling edge, or high level
The bus mastership can be requested by notifying the external bus master that the external
interrupt and on-chip peripheral module interrupt requests have been generated.
Features
Block Diagram
Section 8 Interrupt Controller (INTC)
Rev. 1.00 Dec. 27, 2005 Page 235 of 932
Section 8 Interrupt Controller (INTC)
REJ09B0269-0100
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