HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 263
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 263 of 980
- Download datasheet (6Mb)
Note: W2LOAD and W3LOAD should not be set to 1 at the same time.
Bit
31 to 17
16
15 to 10
9
8
7 to 2
1
0
Bit Name
—
LE
—
W3LOAD
W3LOCK
—
W2LOAD
W2LOCK
Initial
Value
All 0
0
All 0
0
0
All 0
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Lock enable (LE)
Controls cache lock mode.
0: Enters cache lock mode when the DSP bit of the
1: Enters cache lock mode regardless of the DSP bit
Reserved
These bits are always read as 0. The write value
should always be 0.
Way 3 Load (W3LOAD)
Way 3 Lock (W3LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W3LOAD
and W3LOCK in CCR2 are set to 1, the data is
always loaded into way 3. Under any other
condition, the prefetched data is loaded into the way
to which LRU points.
Reserved
These bits are always read as 0. The write value
should always be 0.
Way 2 Load (W2LOAD)
Way 2 Lock (W2LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W2LOAD
and W2LOCK in CCR2 are set to 1, the data is
always loaded into way 2. Under any other
condition, the prefetched data is loaded into the way
to which LRU points.
SR register is set to 1.
value.
Rev. 1.00 Dec. 27, 2005 Page 219 of 932
REJ09B0269-0100
Section 6 Cache
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