HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 232
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 232 of 980
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Section 5 Memory Management Unit (MMU)
Physical Address Space: This LSI supports a 29-bit physical address space. As shown in figure
5.5, the physical address space is divided into eight areas. Area 1 is mapped to the on-chip
module control register area and on-chip memory area. Area 7 is reserved.
For details on physical address space, refer to section 12, Bus State Controller (BSC).
Address Transition: When the MMU is enabled, the virtual address space is divided into units
called pages. Physical addresses are translated in page units. Address translation tables in external
memory hold information such as the physical address that corresponds to the virtual address and
memory protection codes. When an access to area P1 or P2 occurs, there is no TLB access and the
physical address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is
searched by virtual address and, if that virtual address is registered in the TLB, the access hits the
TLB. The corresponding physical address and the page control information are read from the TLB
and the physical address is determined.
If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
Rev. 1.00 Dec. 27, 2005 Page 188 of 932
REJ09B0269-0100
Figure 5.5 External Memory Space
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
H'0000 0000
Register and On-Chip Memories)
(On-Chip module control
(Reserved Area)
Area 0
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Area 1
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