HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 277

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The X/Y memory can be accessed by the
DSP directly from space P2. The MMU can be used to map the logical addresses in spaces P0 and
P3 to this memory.
User DSP mode (SR.MD = 0 and SR.DSP = 1): The X/Y memory can be accessed by the DSP
directly from space Uxy. The MMU can be used to map the logical addresses in space U0 to this
memory.
7.2.3
The X/Y memory is always accessed by the DMAC and E-DMAC via the I bus, which is a
physical address bus. Addresses in which the upper three bits are 0 in addresses shown in table 7.1
must be used.
7.3
7.3.1
In the event of simultaneous accesses to the same page from different buses, the conflict on the
pages occurs. Although each access is completed correctly, this kind of conflict tends to lower
X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such
conflict as far as possible. For example, conflict will not arise if different memory or different
pages are accessed by each bus.
7.3.2
The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I
bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of
conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software
measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory
by the CPU not via the I bus but directly from space P2 or Uxy, conflict on the I bus can be
prevented.
7.3.3
When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled
(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If
the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory
Bus Conflict
Access from DMAC and E-DMAC
Usage Notes
Page Conflict
MMU and Cache Settings
Rev. 1.00 Dec. 27, 2005 Page 233 of 932
Section 7 X/Y Memory
REJ09B0269-0100