HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 181
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 181 of 980
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3.5.11
The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the
SH's standard multiply and MAC operations. The S bit in SR is used as the overflow protection
enable bit. The arithmetic operation overflows when the operation result exceeds the range of
two’s complement representation without guard-bit parts. Table 3.31 shows the definition of
overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed
multiplication described in section 3.5.7, Fixed-Point Multiply Operation. Table 3.32 shows the
definition of overflow protection for integer arithmetic operations. The lower word of the
saturation value of the integer arithmetic operation is don’t care. Lower word value cannot be
guaranteed.
When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the
DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits.
Table 3.31 Definition of Overflow Protection for Fixed-Point Arithmetic Operations
Table 3.32 Definition of Overflow Protection for Integer Arithmetic Operations
Note:
Sign
Positive
Negative
Sign
Positive
Negative
*
Overflow Protection
means don't care.
Overflow Condition
Result > 1 – 2
Result < –1
Overflow Condition
Result > 2
Result < –2
15
15
– 1
–31
Fixed Value
1 – 2
–1
Fixed Value
2
–2
15
15
– 1
–31
Rev. 1.00 Dec. 27, 2005 Page 137 of 1044
Section 3 DSP Operating Unit
Hex Representation
00 7FFF FFFF
FF 8000 0000
Hex Representation
00 7FFF ****
FF 8000 ****
REJ09B0269-0100
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