HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 208
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 208 of 980
- Download datasheet (6Mb)
Section 4 Exception Handling
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
Rev. 1.00 Dec. 27, 2005 Page 164 of 932
REJ09B0269-0100
Exception Type
General exception
events
(asynchronous)
General interrupt
requests
(asynchronous)
2. For details on priorities in multiple interrupt sources, refer to section 8, Interrupt
3. If an interrupt is accepted, the interrupt source register (EXPEVT) is not changed. The
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
5. These exception codes are valid when the MMU is used.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
Controller (INTC).
interrupt source code is specified in interrupt source register 2 (EXPEVT2). For details,
refer to section 8, Interrupt Controller (INTC).
and vector offset are specified.
Current
Instruction
Completed
Completed
Exception Event
User breakpoint
(Data break, I-BUS
break)
DMA address error
Interrupt requests
Priority*
2
2
3
1
Exception
Order
5
6
—*
2
Process
at BL=1
Ignored
Retained
Retained
Vector
Code
H'1E0
H'5C0
—*
3
Vector Offset
H'00000100
H'00000100
H'00000600
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