HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 791

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.2.11 FIFO Depth Register (FDR)
FDR is a 32-bit readable/writable register that specifies the size of the transmit and receive FIFOs.
Bit
31 to 11
10 to 8
7 to 3
2 to 0
Bit Name

TFD2 to
TFD0

RFD2 to
RFD0
Initial
Value
All 0
All 1
All 0
All 1
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Specifies 256 bytes to 2 kbytes in 256-byte units as
the size of the transmit FIFO. The setting must not be
changed after transmission/reception has started.
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive FIFO Size
Specifies 256 bytes to 2 kbytes in 256-byte units as
the size of the receive FIFO. The setting must not be
changed after transmission/reception has started.
Transmit FIFO Size
Rev. 1.00 Dec. 27, 2005 Page 747 of 932
REJ09B0269-0100