HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 130

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
4. Restriction on branching to an instruction following the repeat detection instruction and an
Here, a branch includes a return from an exception processing routine. If an exception whose
return address is placed in an instruction following the repeat detection instruction occurs, the
repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted
from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts
that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a
transition to an exception occurs but a program cannot be returned to the previous execution state
correctly. For details, refer to section 4, Exception Handling.
Notes: 1. If a TRAPA instruction is used as a repeat detection instruction, an instruction
5. Branch from a repeat detection instruction
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exception acceptance
CPU can recognize the repeat loop. Therefore, when the execution branches to an instruction
following the repeat detection instruction, the control will not be passed to a repeat start
instruction after executing a repeat end instruction because the repeat loop is not recognized by
the CPU. In this case, the RC[11:0] bits of the SR register will not be changed.
 If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
 If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine
If a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a
branch instruction, a repeat loop can be acknowledged when a branch does not occur in a
branch instruction. If a branch occurs in a branch instruction, a repeat control is not performed
and a branch destination instruction is executed.
Execution of a repeat detection instruction must be completed without any branch so that the
detection instruction must be specified as a branch destination.
call instruction must be placed before a repeat detection instruction.
2. If a SLEEP instruction is placed following a repeat detection instruction, a transition to
following the repeat detection instruction is regarded as a return address. In this case, a
control cannot be returned to the repeat control correctly. In a TRAPA instruction, an
address of an instruction following the repeat detection address is regarded as return
address. Accordingly, to return to the repeat control correctly, place a return address
prior to the repeat detection instruction.
the low-power consumption state or an exception acceptance such as interrupts can be
performed correctly. In this case, however, the repeat control cannot be returned
correctly. To return to the repeat control correctly, the SLEEP instruction must be
placed prior to the repeat detection instruction.