HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 622
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 622 of 980
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Section 16 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below.
1. The SCIF internally initializes in synchronization with the synchronous clock input or output.
2. The SCIF stores receive data in SCRSR in order from LSB to MSB. After reception, the SCIF
3. If the RDF flag is set to 1 and the RIE bit in SCSCR is set to 1, the SCIF requests a receive-
Rev. 1.00 Dec. 27, 2005 Page 578 of 932
REJ09B0269-0100
checks whether receive data can be transmitted from SCRSR to SCFRDR. If this check is
passed, the SCIF stores the receive data in SCFRDR. If an overrun error is detected by an error
check, following reception can not be performed.
FIFO-data-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit or REIE bit in
SCSCR is set to 1, the SCIF requests a break interrupt (BRI).
Figure 16.16 Sample Serial Reception Flowchart
No
Clear ORER flag in SCLSR to 0
Overrun error handling
Error handling
ORER = 1?
End
Yes
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