HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 820

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.4
19.4.1
[Problems]
While the Ethernet functions are being used, the TR bit in EDTRR or the RR bit in EDRRR is
cleared to 0 to stop the E-DAMC functions if the descriptor valid bit is invalid. When the request
bit (TR or RR) is cleared by the E-DMAC and the request bit (TR or RR) is set by the user's
firmware simultaneously, transmission or reception may not be started even if the request bit (TR
or RR) is set to 1.
[Occurring Condition]
When the user's firmware tries to set the request bit (TR or RR), while the request bit (TR or RR)
is 1.
[Avoiding Methods]
To prevent the simultaneous occurrence of the request bit (TR or RR) being cleared by the E-
DMAC and the request bit (TR or RR) being set by the user's firmware, the user's firmware should
set the request bit (TR or RR) after confirming that it is cleared by the E-DMAC.
The methods to clear the RR bit with E-DMAC are as follows.
(1)
As a direct method, it is possible to confirm by reading the TR bit in EDTRR as 0.
As an indirect method, it is possible to confirm by reading the TDE bit in EESR as 1.
(2)
As a direct method, it is possible to confirm by reading the RR bit in EDRRR as 0.
As an indirect method, it is possible to confirm by reading the RDE bit in EESR as 0.
Rev. 1.00 Dec. 27, 2005 Page 776 of 932
REJ09B0269-0100
Confirmation of the TR bit
Confirmation of the RR bit
Usage Notes
Using of EDTRR and EDRRR