HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 334
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 334 of 980
- Download datasheet (6Mb)
Section 9 User Break Controller
• Register specifications
Break Condition Specified for L Bus Data Access Cycle:
• Register specifications
Rev. 1.00 Dec. 27, 2005 Page 290 of 932
REJ09B0269-0100
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
A user break occurs after an instruction with ASID = H’80 and addresses H'00008000 to
H'00008FFE is executed or before an instruction with ASID = H’70 and addresses H'00008010
to H'00008016 are executed.
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: L bus/data access/read (operand size is not included in the condition)
<Channel B>
Address:
Data:
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from ASID = H’80 and address
H'00123454, word read from address H'00123456, or byte read from address H'00123456. On
channel B, a user break occurs when word H'A512 is written in ASID = H’70 and addresses
H'000ABC00 to H'000ABCFE.
H'00008404, Address mask: H'00000FFF, ASID = H'80
included in the condition)
H'00008010, Address mask: H'00000006, ASID = H'70
H'00000000, Data mask: H'00000000
included in the condition)
H'00123456, Address mask: H'00000000, ASID = H’80
H'000ABCDE, Address mask: H'000000FF, ASID = H’70
H'0000A512, Data mask: H'00000000
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