HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 244
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Memory Management Unit (MMU)
5.4
5.4.1
There are two kinds of MMU hardware management as follows.
1. The MMU decodes the virtual address accessed by a process and performs address translation
2. In address translation, the MMU receives page management information from the TLB, and
5.4.2
There are three kinds of MMU software management, as follows.
1. MMU register setting
2. TLB entry recording, deletion, and reading
3. MMU exception processing
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be created in the privileged mode only.
Rev. 1.00 Dec. 27, 2005 Page 200 of 932
REJ09B0269-0100
by controlling the TLB in accordance with the MMUCR settings.
determines the MMU exception and whether the cache is to be accessed (using the C bit). For
details of the determination method and the hardware processing, see section 5.5, MMU
Exceptions.
MMUCR setting, in particular, should be performed in areas P1 and P2 for which address
translation is not performed. Also, since SV and IX bit changes constitute address translation
system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to
the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the
AT bit cleared to 0, use in the disabled state must be avoided with software that does not use
the MMU.
TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing
directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory
allocation TLB can be accessed. See section 5.4.3, MMU Instruction (LDTLB), for details of
the LDTLB instruction, and section 5.6, Memory-Mapped TLB, for details of the memory-
mapped TLB.
When an MMU exception is generated, it is handled on the basis of information set from the
hardware side. See section 5.5, MMU Exceptions, for details.
MMU Functions
MMU Hardware Management
MMU Software Management
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