HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 262

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Cache
6.2.2
The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU
enters the cache lock mode when the DSP bit (bit 12) in the status register (SR) is set to 1 or the
lock enable bit (bit 16) in the cache control register 2 (CCR2) is set to 1. The cache locking
mechanism is disabled in non-cache lock mode (DSP bit = 0).
When a prefetch instruction (PREF@Rn) is issued in cache lock mode and a cache miss occurs,
the line of data pointed to by Rn will be loaded into the cache, according to the setting of bits 9
and 8 (W3LOAD, W3LOCK) and bits 1 and 0 (W2LOAD, W2LOCK in CCR2).
Table 6.2 shows the relationship between the settings of bits and the way that is to be replaced
when the cache is missed by a prefetch instruction.
On the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the
cache and the valid entry is held. For example, a prefetch instruction is issued while bits
W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0,
the cache is hit and new data is not loaded into way 3.
In cache lock mode, bits W3LOCK and W2LOCK restrict the way that is to be replaced, when
instructions other than the prefetch instruction are issued. Table 6.3 shows the relationship
between the settings of bits in CCR2 and the way that is to be replaced when the cache is missed
by instructions other than the prefetch instruction.
Programs that change the contents of the CCR2 register should be placed in address space that is
not cached.
Rev. 1.00 Dec. 27, 2005 Page 218 of 932
REJ09B0269-0100
Bit
0
Cache Control Register 2 (CCR2)
Bit Name
CE
Initial
Value
0
R/W
R/W
Description
Cache Enable
Indicates whether the cache function is used.
0: The cache function is not used.
1: The cache function is used.