HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 385

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12.4
The BSC has the following registers. Refer to section 23, List of Registers, for the addresses and
access size for these registers.
Do not access spaces other than CS0 until the termination of the setting the memory interface.
• Common control register (CMNCR)
• Bus control register for area 0 (CS0BCR)
• Bus control register for area 2 (CS2BCR)
• Bus control register for area 3 (CS3BCR)
• Bus control register for area 4 (CS4BCR)
• Bus control register for area 5A (CS5ABCR)
• Bus control register for area 5B (CS5BBCR)
• Bus control register for area 6A (CS6ABCR)
• Bus control register for area 6B (CS6BBCR)
• Wait control register for area 0 (CS0WCR)
• Wait control register for area 2 (CS2WCR)
• Wait control register for area 3 (CS3WCR)
• Wait control register for area 4 (CS4WCR)
• Wait control register for area 5A (CS5AWCR)
• Wait control register for area 5B (CS5BWCR)
• Wait control register for area 6A (CS6AWCR)
• Wait control register for area 6B (CS6BWCR)
• SDRAM control register (SDCR)
• Refresh timer control/status register (RTCSR)*
• Refresh timer counter (RTCNT)*
• Refresh time constant register (RTCOR)*
• SDRAM mode register for area 2 (SDMR2)*
• SDRAM mode register for area 3 (SDMR3)*
Notes: 1. This register only accepts 32-bit writing to prevent incorrect writing. In this case, the
2. The contents of this register are stored in SDRAM. When this register space is
Register Descriptions
upper 16 bits of the data must be H'A55A. Otherwise, writing cannot be performed. In
reading, the upper 16 bits are read as H'0000.
accessed, the corresponding register in SDRAM is written to. For details, see
description of Power-on Sequence in section 12.5.5, SDRAM Interface.
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Rev. 1.00 Dec. 27, 2005 Page 341 of 932
Section 12 Bus State Controller (BSC)
REJ09B0269-0100