HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 784

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.7
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit.
Rev. 1.00 Dec. 27, 2005 Page 740 of 932
REJ09B0269-0100
Bit
31
30
29 to 27
26
25
24
23
22
21
EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
Bit Name

TWBIP

TABTIP
RABTIP
RFCOFIP
ADEIP
ECIIP
TCIP
Initial
Value
0
0
All 0
0
0
0
0
0
0
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Abort Detection Interrupt Enable
0: Transmit abort detection interrupt is disabled
1: Transmit abort detection interrupt is enabled
Receive Abort Detection Interrupt Enable
0: Receive abort detection interrupt is disabled
1: Receive abort detection interrupt is enabled
Receive Frame Counter Overflow Interrupt Enable
0: Receive frame counter overflow interrupt is disabled
1: Receive frame counter overflow interrupt is enabled
Address Error Interrupt Enable
0: Address error interrupt is disabled
1: Address error interrupt is enabled
EtherC Status Register Interrupt Enable
0: EtherC status interrupt is disabled
1: EtherC status interrupt is enabled
Frame Transmit Complete Interrupt Enable
0: Frame transmit complete interrupt is disabled
1: Frame transmit complete interrupt is enabled