HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 220

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Handling
SPC Saved by Exception in Repeat Control Period: If an exception is accepted in the repeat
control period while the repeat counter (RC[11:0]) in the SR register is two or greater, the program
counter to be saved may not indicate the value to be returned correctly. To execute the repeat
control after returning from an exception processing, the return address must indicate an
instruction prior to a repeat detection instruction. Accordingly, if an exception is accepted in
repeat control period, an exception other than re-execution type exception by a repeat detection
instruction cannot return to the repeat control correctly.
Table 4.3
Note: The following labels are used here.
Illegal Instruction Exception in Repeat Control Period: If one of the following instructions is
executed at the address following RptDtct1, a general illegal instruction exception occurs. For
details on an address to be saved in the SPC, refer to the description in section 4.4.3, Exception in
Repeat Control Period.
• Branch instructions
• Repeat control instructions
• Load instructions for SR, RS, and RE
Rev. 1.00 Dec. 27, 2005 Page 176 of 932
REJ09B0269-0100
Instruction where
Exception Occurs
RptDtct
RptDtct1
RptDtct2
RptDtct3
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
SETRC, LDRS, LDRE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,Rs
RptDtct:
RptDtct1: An instruction address one instruction following the repeat detection instruction
RptDtct2: An instruction address two instruction following the repeat detection instruction
RptDtct3: An instruction address three instruction following the repeat detection instruction
RS:
If a re-execution type exception is accepted at an instruction in the hatched areas above, a
return address to be saved in the SPC is incorrect. If RC[11:0] is 1 or 0, a correct return
address is saved in the SPC.
SPC Value when Re-Execution Type Exception Occurs in Repeat Control
(RC[11:0] ≥ 2)
Repeat detection instruction address
Repeat start instruction address
1
RptDtct
RptDtct1


Number of Instructions in Repeat Loop
2
RptDtct
RptDtct1
RptDtct1

RptDtct
RptDtct1
RptDtct1
RptDtct1
3
4 or Greater
RptDtct
RptDtct1
RS-4
RS-2