HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 798

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.3.1
Descriptors and Descriptor List
Two types of descriptors are available: transmit descriptors and receive descriptors. The E-DMAC
automatically starts reading a transmit/receive descriptor when the TR bit in EDTRR is set to 1 or
the RR bit in EDRRR is set to 1. In a transmit/receive descriptor, the user stores information about
DMA transfer of transmit/receive data. After completion of Ethernet frame transmission/reception,
the E-DMAC disables the descriptor valid/invalid bit and reflects the result of
transmission/reception in the status bits.
Descriptors are placed in a readable/writable memory space. The address of the start descriptor
(descriptor to be read first by the E-DMAC) is set in TDLAR/RDLAR. When multiple descriptors
are prepared as a descriptor row (descriptor list), the descriptors are placed in continuous
(memory) addresses according to the descriptor length set in the DL0 and DL1 bits in EDMR.
The E-DMAC consists of two systems: system 0 and system 1. The DMAC for transmission and
the DMAC for reception operate independently of each other, and the DMAC for system 0 and the
DMAC for system 1 operate independently of each other. For normal E-DMAC operation, place
descriptors for transmission and reception and descriptors for system 0 and system 1 in those
address spaces that do not overlap.
(1)
Transmit Descriptor
Figure 19.2 shows the configuration of a transmit descriptor and the relationship with a transmit
buffer.
The data of a transmit descriptor consists of TD0, TD1, TD2, and padding data in groups of 32
bits from top to end. The length of padding data is determined according to the descriptor length
specified by the DL0 and DL1 bits in EDMR. In the figure, TBA (bits 31 to 0 in TD2) indicates
the start address of a transmit buffer, and TDL (bits 31 to 16 in TD1) indicates the valid data
length of the transmit buffer.
TD0 indicates whether the transmit descriptor is valid or invalid as well as information about the
descriptor configuration and status. TD1 indicates the length of data in a transmit buffer to be
transferred according to the specification of the descriptor. TD2 indicates the start address of a
transmit buffer that holds data to be transferred.
Depending on the descriptor specification, one transmit descriptor can specify all transmit data of
one frame (single-frame/single-buffer) or multiple descriptors can specify the transmit data of one
frame (single-frame/multi-buffer). As an example of single-frame/multi-buffer operation, the data
portion that is used in a fixed manner in each Ethernet frame transmission can be referenced by
multiple descriptors. For example, multiple descriptors can share the destination address and
Rev. 1.00 Dec. 27, 2005 Page 754 of 932
REJ09B0269-0100